ArchExplorer for Automatic Design Space Exploration

Loop Controller Area Estimation for Automatic Design Space Exploration

High-level synthesis systems overcome the high design effort required to program an FPGA by translating an algorithm at the behavioral level into a synthesizable hardware description. At this higher level, loop transformations are used to improve the characteristics of the program. These transformations have a great impact on the resulting hardware, only known after the time-consuming synthesis...

Automatic Exploration and Characterization of the Cluster Design Space

A cluster is a parallel supercomputer built using interchangeable parts. Not only do many of the components benefit from commodity pricing, reducing system cost, but it also becomes practical to customize the architectural configuration with a breadth of choices that was unimaginable just a few years ago. At SC2002, we introduced the Cluster Design Rules (CDR), a software tool which helps users...

A Power Aware Cache and Register File Design Space Exploration

Accelerating Design Space Exploration∗

The size of search spaces in embedded system design is one of the most critical problems during design space exploration. Pareto-Front Arithmetics (PFA) has shown to be useful to overcome this problem by decomposing a hierarchical search space and just exploring each part of the system separately. Later, the exploration results are combined at higher levels of the hierarchy. In order to decreas...

Exploration in Design Space

The methodology of AI as the general study of natural and artiicial intelligence is outlined, including exploration of designs for a variety of behaving systems, for both scientiic and engineering purposes. Thèdesign-stance' treats minds as sophisticated self-monitoring, self-modifying control systems. Diierent architectures can satisfy that description. Exploration of possible requirements and...